This invention relates generally to a memory bus architecture, and in particular to a single memory bus capable of communicating data and programming signals to an expandable and reconfigurable system memory.
Modern electronic computer systems utilize memory to store instructions and data which are necessary to make the computer function properly. The memory which stores instructions and data is referred to as system memory. System memory is often made up of a mix of different memory types to fulfill a variety of requirements. One common memory type is programmable read only (PROM) memory. PROM memory is often used to store the initial code for starting the computer, commonly referred to as boot code. Another common memory type is dynamic random access (DRAM) memory. DRAM memory provides fast data storage and retrieval times and is commonly used to during computer operation. A third type of memory is referred to as disk memory. Disk memory typically provides a very large storage space and is used to store the programs that are loaded into the DRAM memory as well as other large blocks of computer information. A fourth type of memory is serial memory. Serial memory is often used to store the last state of the computer system and therefore is not required to be large in size or fast in execution.
The various elements of system memory are normally placed in different physical locations in the computer system. For instance, the PROM and serial memory may be in semiconductor devices placed on the same board next to the host computer central processing unit (CPU). DRAM memory may reside on removable cards called DIMM or SIMM modules that are then inserted into sockets physically near the CPU. The disk memory may be in a semi-removable enclosure physically separated some distance from the CPU.
Data is communicated between the CPU and the system memory over one or more memory buses. One known bus architecture uses separate buses, each connected to a different memory type within the system memory. As shown in FIG. 1, a general purpose memory bus 25 connects the CPU 10 to the PROM memory 30, while a high speed DRAM bus 15 connects CPU 10 to the DRAM memory 20. The CPU 10 may be connected to its disk memory 40 indirectly through a controller 35 which itself is connected to the general purpose system bus 25. The CPU 10 may be connected to the serial memory 45 using a serial bus 47.
Typically, each bus has a protocol which defines how information is communicated between the CPU and the connected memory device. The general purpose bus 25, for instance, may employ a protocol which requires transmission of acknowledgment signals between the CPU and the system memory as an indication that the desired data has been received. In contrast, the bus connecting the CPU and DRAM memory may not require acknowledgment signals which, in some cases, tend to slow down data transfer.
The multiple memory bus architecture of FIG. 1 provides the advantages of reliable and fast data transfer through the use of dedicated memory buses. However, the multiple bus architecture is costly since its implementation often requires redundant use of the CPU signal lines and multiple connectors to the various memory devices. Further, because each memory type may employ some programmable memory devices and each memory type is accessed through separate bus lines requiring different protocols, programming these memory devices is often complicated and time consuming.
What is needed is a single memory bus architecture which can carry data and provide programming access to each memory device used within the system memory. Further advantageous would be a single memory bus which could accommodate additional or different types of memory devices subsequently added to the system memory. Providing the attributes of data and programming accessibility over a single memory bus enables the placement of the entire system memory on one or more physically and electrically similar universal memory cards. With the system memory residing on universal memory card(s), the user can easily configure the initial system memory and, if the need arises, reconfigure or upgrade the system memory to meet future system memory requirements.